;*******************************************************************************
;Aleix Riera
;www.fjarre.com/~aleix
;aleix@fjarre.com
;*******************************************************************************
;------------------------------------------------------------------------------
; ConfigureAudioDMA
; This routine configures DMA channels 0 and 1 for audio transmitter and
; receiver
;------------------------------------------------------------------------------
ConfigureAudioDMA:
	;**********************************************************************
	; Disable ESSI0 transmitter and receiver 
	;**********************************************************************
	BCLR	#CRB_TE0,X:<<CRB0
	BCLR	#CRB_RE,X:<<CRB0

	;**********************************************************************
	; Disable DMA Channels 0 and 1
	;**********************************************************************
	BCLR	#DCR_DE,X:<<DCR0
	BCLR	#DCR_DE,X:<<DCR1

	;**********************************************************************
	; DOR0: DMA OFFSET REGISTER 0 (DSP56300FM page 8-3)
	; Offset: -(2*2*BUFFER_SIZE-1)
	;**********************************************************************
	MOVEP	#>-(2*2*BUFFER_SIZE-1),X:<<DOR0

	;**********************************************************************
	; DCO0: DMA COUNTER CHANNEL 0 (DSP56300FM page 8-5)
	; DCOL: 0
	; DCOH: 2*2*BUFFER_SIZE-1
	;**********************************************************************
	MOVEP	#>(2*2*BUFFER_SIZE-1),X:<<DCO0

	;**********************************************************************
	; DSR0: DMA SOURCE ADDRESS REGISTER CHANNEL 0 (DSP56300FM page 8-2)
	;**********************************************************************
	MOVEP	#>BufferDAC,X:<<DSR0

	;**********************************************************************
	; DDR0: DMA DESTINATION ADDRESS REGISTER CHANNEL 0 (DSP56300FM page 8-2)
	;**********************************************************************
	MOVEP	#>TX00,X:<<DDR0

	;**********************************************************************
	; DCR0: DMA CONTROL REGISTER CHANNEL 0 (DSP56300FM page 8-8)
	; DMA Source Space: X mem				(00)
	; DMA Destination Space: X mem				(00)
	; DMA Address Mode: Mode B, DOR0, src 2D, dst no update(100000)
	; DMA Three Dimensional Mode: Off			(0)
	; DMA Request Source: ESSI0Tx				(01011)
	; DMA Continuous Mode					(0)
	; DMA Channel Priority: 3				(11)
	; DMA Transfer Mode: word transfer, no clear DE	(101)
	; DMA Interrupt Enable: Off				(0)
	; DMA Channel Enable: Off				(0)
	;**********************************************************************
	; 0 0 101 11 0 01011 0 100000 00 00 = 0x2E5A00
	;**********************************************************************
	MOVEP	#>$2E5A00,X:<<DCR0

	;**********************************************************************
	; DOR1: DMA OFFSET REGISTER 1 (DSP56300FM page 8-3)
	; Offset: -(2*2*BUFFER_SIZE-1)
	;**********************************************************************
	MOVEP	#-(2*2*BUFFER_SIZE-1),X:<<DOR1

	;**********************************************************************
	; DCO1: DMA COUNTER CHANNEL 1 (DSP56300FM page 8-5)
	; DCOL: 0
	; DCOH: 2*2*BUFFER_SIZE-1
	;**********************************************************************
	MOVEP	#>(2*2*BUFFER_SIZE-1),X:<<DCO1

	;**********************************************************************
	; DDR1: DMA DESTINATION ADDRESS REGISTER CHANNEL 1 (DSP56300FM page 8-2)
	;**********************************************************************
	MOVEP	#>BufferADC,X:<<DDR1

	;**********************************************************************
	; DSR1: DMA SOURCE ADDRESS REGISTER CHANNEL 1 (DSP56300FM page 8-2)
	;**********************************************************************
	MOVEP	#>RX0,X:<<DSR1

	;**********************************************************************
	; DCR1: DMA CONTROL REGISTER CHANNEL 1 (DSP56300FM page 8-8)
	; DMA Source Space: X mem				(00)
	; DMA Destination Space:X mem				(00)
	; DMA Address Mode: Mode B, DOR1, dst 2D, src no update(001100)
	; DMA Three Dimensional Mode: Off			(0)
	; DMA Request Source: ESSI0Rx				(01010)
	; DMA Continuous Mode					(0)
	; DMA Channel Priority: 3				(11)
	; DMA Transfer Mode: word transfer, no clear DE	(101)
	; DMA Interrupt Enable: Off				(0)
	; DMA Channel Enable: Off				(0)
	;**********************************************************************
	; 0 0 101 11 0 01010 0 001100 00 00 = 0x2E50C0
	;**********************************************************************
	MOVEP	#>$2E50C0,X:<<DCR1

	;**********************************************************************
	; Initialize active buffer to 2, so the first filled will be 1
	;**********************************************************************
	MOVE	#>BufferDAC2,X0
	MOVE	X0,Y:ActiveBufferDAC
	MOVE	#>BufferADC2,X0
	MOVE	X0,Y:ActiveBufferADC

	;**********************************************************************
	; Empty ADC and DAC buffers
	;**********************************************************************
	CLR	A

	MOVE	#BufferDAC,R0
	REP	#(2*2*BUFFER_SIZE)	; 2 DAC stereo consecutive buffers
	  MOVE	A,X:(R0)+

	MOVE	#BufferADC,R0
	REP	#(2*2*BUFFER_SIZE)	; 2 DAC stereo consecutive buffers
	  MOVE	A,X:(R0)+

	;**********************************************************************
	; Enable ESSI0 transmitter and receiver 
	;**********************************************************************
	MOVEP	A,X:<<TX00
	BSET	#CRB_TE0,X:<<CRB0
	BSET	#CRB_RE,X:<<CRB0

	;**********************************************************************
	; Synchronize DMA Transmitter buffers with audio left and right
	;**********************************************************************
	BRCLR	#SSISR_TDE,X:<<SSISR0,*
	BRSET	#SSISR_TFS,X:<<SSISR0,_ConfigureAudioDMALabel1
	MOVEP	A,X:<<TX00
	BRCLR	#SSISR_TDE,X:<<SSISR0,*
_ConfigureAudioDMALabel1:
	MOVEP	A,X:<<TX00
		
	;**********************************************************************
	; Enable DMA Channel 0 (ESSI0 TX)
	;**********************************************************************
	BSET	#DCR_DE,X:<<DCR0

	MOVEP	X:<<RX0,A
	BRCLR	#SSISR_RDF,X:<<SSISR0,*
	BRSET	#SSISR_RFS,X:<<SSISR0,_ConfigureAudioDMALabel2
	MOVEP	X:<<RX0,A
	BRCLR	#SSISR_RDF,X:<<SSISR0,*
_ConfigureAudioDMALabel2:

	;**********************************************************************
	; Enable DMA Channel 1 (ESSI0 RX)
	;**********************************************************************
	BSET	#DCR_DE,X:<<DCR1
	
	RTS